Abstract :

Scan architecture is a widely used design modification for testability in ASICs to obtain good test coverage. But during the process of scan testing, power consumption is much higher than in functional mode of operation, as all the flops in the design switch during scan shift operations (shift-in and shift-out). The heat generated from high power dissipation can destroy the chip, cause reliability problems, or induce noise. Sometimes the problem of wrong response due to overheating may arise, causing yield loss. For these reasons, test power reduction is a topic for research. Though there are several scan shift power optimization techniques used in practice, scan chain stitching techniques based on logic topology proposed in the recent years address both shift-in and shift-out powers. Conceptually, the techniques likely cause routing congestion and therefore applying the techniques under a routing constraint could be an optimal solution is the proposal presented in this paper.

---

Keywords :

Routing congestion, scan chain, Scan testing, shift-in and shift-out power, Test power.

---

References :

1. Wang, K. S. Li, S. Chen, H. Shiu and Y. Chu, “Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 5, pp. 716-727, May 2009, doi: 10.1109/TCAD.2009.2015741.
2. Pathak, A. Grover, M. Pohit and N. Bansal, “LoCCo-Based Scan Chain Stitching for Low-Power DFT,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3227-3236, Nov. 2017, doi: 10.1109/TVLSI.2017.2735864.
3. Lee, K. Cho, S. Choi and S. Kang, “A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3432-3436, Dec. 2020, doi: 10.1109/TCSII.2020.3004371.
4. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch and A. Virazel, “Design of routing-constrained low power scan chains,” Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications, 2004, pp. 287-292, doi: 10.1109/DELTA.2004.10009.
5. Cui, T. Yu, G. Qu and M. Li, “An improved scan design for minimization of test power under routing constraint,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 629-632, doi: 10.1109/ISCAS.2015.7168712.
6. S. Li, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, pp. 618-626, April 2010, doi: 10.1109/TCAD.2010.2042896.
7. Seo et al., “Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction,” 2015 IEEE 24th Asian Test Symposium (ATS), 2015, pp. 1-6, doi: 10.1109/ATS.2015.8.
8. Shaktisinh, J. Popat and R. Patel, “Power reduction techniques used in testing of VLSI circuits,” 2015 Annual IEEE India Conference (INDICON), 2015, pp. 1-4, doi: 10.1109/INDICON.2015.7443367.
9. ElShoukry, M. Tehranipoor and C. P. Ravikumar, “Partial Gating Optimization for Power Reduction During Test Application,” 14th Asian Test Symposium (ATS’05), 2005, pp. 242-247, doi: 10.1109/ATS.2005.87.
10. Bushnell and V. Agrawal, “Essentials of Electronic Testing for digital, memory and mixed-signal,” Kluwer Academic, 2000, pp. 14.